1. Field of the Invention
The present invention relates to a class-AB push-pull drive circuit used for an audio circuit and the like and more particularly to the expansion of an operating range of an output voltage thereof.
2. Description of the Prior Art
FIG. 3 is a circuit diagram showing a conventional push-pull drive circuit. As shown in FIG. 3, an input terminal 1 is connected to the gate of an N channel MOS transistor Q.sub.10. The source of the transistor Q.sub.10 is grounded, and the drain thereof is connected to the gate of a P channel MOS transistor Q.sub.1 and to the drain of a P channel MOS transistor Q.sub.9 in which the gate and the drain are connected in common. The source of the transistor Q.sub.9 is connected to the source of an N channel MOS transistor Q.sub.8. The drain of the transistor Q.sub.8 is connected to the gate of an N channel MOS transistor Q.sub.2 and to one end of a resistor R.sub.3. The and gate of trasistor Q.sub.8 is connected to the other end of the resistor R.sub.3. The other end of the resistor R.sub.3 is connected through a constant current source I.sub.4 to the positive side of a DC power source 3. The negative side of the DC power source 3 is grounded. The source of the transistor Q.sub.1 is connected to an output terminal 2, and the drain thereof is grounded. The source of the transistor Q.sub.2 is connected to the output terminal 2, and the drain thereof is connected to the positive side of the DC power source 3.
If a gate-source voltage of the transistor Q.sub.8 is designated by V.sub.GS8, a gate-source voltage of the transistor Q.sub.9 by V.sub.GS9, drain currents of the transistors Q.sub.8 and Q.sub.9 by I.sub.B4, a gate-source voltage of the transistor Q.sub.2 by V.sub.GS2, a drain current thereof by I.sub.D2, a gate-source voltage of the transistor Q.sub.1 by V.sub.GS1, and a drain current thereof by I.sub.D1, the following equations hold: ##EQU1## where .beta..sub.8 is a constant determined by the configuration of the transistor Q.sub.8, .beta..sub.9 is a constant determined by the configuration of the transistor Q.sub.9, .beta..sub.2 is a constant determined by the configuration of the transistor Q.sub.2, .beta..sub.1 is a constant determined by the configuration of the transistor Q.sub.1, V.sub.THON is a threshold voltage of the N channel transistors, and V.sub.THOP is a threshold voltage of the P channel transistors.
With respect to a potential difference between the gate of the transistor Q.sub.2 and the gate of the transistor Q.sub.3, the following equation holds: EQU V.sub.GS2 +V.sub.GS1 =V.sub.GS8 +V.sub.GS9 -R.sub.3 I.sub.B4( 5)
where R.sub.3 is a resistance value of the resistor R.sub.3, and I.sub.B4 is a bias current from the constant current source I.sub.4.
As is obvious from the equations (5), (1) and (2), the potential difference between the gates of the transistors Q.sub.1 and Q.sub.2 can be held constant by setting R.sub.3 and I.sub.B4 appropriately.
When the equations (1), (2), (3) and (4) are substituted in the equation (5), the following equation holds: ##EQU2## where I.sub.B3 is a constant bias current supplied from a constant current source I.sub.3. The value on the right side of the equation (6) is constant independently of the drain currents I.sub.D1 and I.sub.D2 of the transistors Q.sub.1 and Q.sub.2 in an output stage. Accordingly, it can be expressed as follows: ##EQU3##
If the current which flows from the drain of the transistor Q.sub.2 to the drain of the transistor Q.sub.1, while no load current is present in the output terminal 2, is designated by I.sub.idle, I.sub.idle =I.sub.D1 =I.sub.D2 the following equation holds: ##EQU4## This current value can be held sufficiently small by increasing the resistance value R.sub.3.
When load is connected to the output terminal 2 and an outflow current I.sub.source is present, the gate-source voltage V.sub.GS2 of the transistor Q.sub.2 is increased. In such a case, because the voltage between the gates of the transistors Q.sub.1 and Q.sub.2 is constant as expressed by the equation (5), the gate-source voltage V.sub.GS1 of the transistor Q.sub.1 is decreased and, as a result, the drain current I.sub.D1 of the transistor Q.sub.1 is decreased.
In this state, if the drain current I.sub.D1 of the transistor Q.sub.1 is disregarded, an increasable maximum voltage V.sub.2max of the output terminal 2 can be found by the following equations: ##EQU5## where E is a voltage value of the DC power source 3.
In a normal enhancement CMOS structure, V.sub.THON is about 0.8V. For sufficient current flow in the transistor Q.sub.2, .sqroot.2I.sub.source /.beta..sub.2 must be about 0.5 V. According to the equation (10), the increasable maximum voltage V.sub.2max of the output terminal 2 is less than the voltage value obtained by subtracting 1.3 V from the source voltage E.
When a load is connected to the output terminal 2 and an inflow current I.sub.sink is present, the gate-source voltage V.sub.GS1 of the transistor Q.sub.1 is increased. Also in this case, because the voltage between the gates of the transistors Q.sub.2 and Q.sub.1 is constant as expressed by the equation (5), the gate-source voltage V.sub.GS2 of the transistor Q.sub.2 is decreased and, as a result, the drain current I.sub.D2 of the transistor Q.sub.2 is decreased.
In this state, if the drain current I.sub.D2 of the transistor Q.sub.2 is disregarded, an decreasable minimum voltage V.sub.2min of the output terminal 2 can be found by the following equations: ##EQU6##
In the normal enhancement CMOS structure, V.sub.THOP is about 0.8 V. For sufficient current flow in the transistor Q.sub.1, .sqroot.2I.sub.sink /.beta..sub.1 must be about 0.5 V. According to the equation (12), the decreasable minimum voltage V.sub.2min of the output terminal 2 is more than 1.3 V.
In the conventional class-AB push-pull drive circuit as constructed above, the attainable maximum and minimum output voltages from the output terminal 2 are (E-1.3)V and 1.3 V respectively, and therefore there has been a problem that the operating range of the output voltage is narrow.